Electrostatic discharge (ESD) events cause numerous problems in the field of integrated circuits. The semiconductor industry has devoted a substantial amount of funds and effort into reducing the damage to integrated circuits caused by ESD events. The problems associated with an ESD event include high voltages that result in large electric fields and current densities in small semiconductor devices, such as integrated circuits. Research conducted by the semiconductor industry has shown that a fair percentage of integrated circuit failures are attributable to ESD events.
A background and history of electrostatic discharge is described in ESD in Silicon Integrated Circuits, by A. Amerasekera et al., Texas Instruments Inc., USA (2000), pp. 1-4, 9-15. The static discharge associated with ESD events usually accumulates from handling of the integrated circuits by humans or contact with machines that are used to fabricate integrated circuits. The voltages associated with a typical ESD event can range from 500 volts to potentially 20,000 volts. Typically, an ESD event will last about 100 nanoseconds (ns) with peak currents in the ampere range. The resulting electrostatic discharge has enough energy to cause the failure of electronic devices and components. Damage to the integrated circuits is usually caused by the high thermal energies created by the current discharging through current paths created by high voltage breakdown mechanism during the electrostatic discharge event.
During integrated circuit manufacturing and handling, electrostatic discharge events commonly arise from three sources. The most common is human handling, wherein a person walking across a synthetic floor surface, such as a vinyl floor, can accumulate an electrostatic charge of up to 20 kV. Once the person touches an object of sufficient size, the charge accumulated on the person will discharge from the person to the object. The object is effectively at ground potential when the person touches it. The second source of ESD is during the automatic test and the handling of the integrated circuits during the manufacturing process. As the equipment used to test and handle the integrated circuits moves through its handling and testing routine, if the equipment is improperly grounded, an electrostatic charge can accumulate. The accumulated electrostatic charge will then be discharged when the test and handling equipment contacts the integrated circuits. Finally, it is possible that the integrated circuit (IC) itself will become charged when transported or if it comes in contact with a charged surface or material. If the IC becomes charged, it may remain charged until it comes in contact with a grounded surface, in which case, it will discharge through its pins and potentially create large voltages and currents within the device, resulting in damage to the IC.
The semiconductor industry has developed models to study the impact of the electrostatic discharges based on different criteria. Two of the models are the human body model and the machine model.
The human body model is an ESD testing standard and is used to simulate the ESD event that results from human handling of the integrated circuit. The human body model uses a 100 pF capacitor which is typically charged to 2000 volts at which point the capacitor is discharged through a 1500 ohm resistor and the connecting pins of the integrated circuit or device under test. During the simulated ESD event of the human body model, the discharge time in which the peak current is seen is approximately 10 ns and the decay time is around 150 ns. However, the ESD event can have a duration of approximately 200-500 ns.
The machine model uses a 200 pF capacitor which is typically charged to 200 volts. The capacitor is then discharged through a zero ohm resistor and the pins of the IC or device under test. The effective discharge time of the current is about 15 ns and, depending upon different values used in the model, the discharge time can be up to 30 ns. The two models have a similar decay time of about 150 ns. However, ESD event durations have been known to last up to 1000 ns.
The currents generated by the human body model can be up to 1.5 A, while the machine model generates current up to approximately 3 A, both of which can cause damage to circuitry.
Using the above described models, different ESD protection circuits provide varying time periods to protect against multiple ESD events, and attempt to maintain protection for a longer duration of time, which can last up to approximately 1000 ns.
Prior art systems have been seen where an electrostatic discharge event occurs and a clamping circuit initially limits the amount of ESD voltage seen by the protected device. The basic concept of the ESD clamping device 10, as shown in FIG. 1, comprises an RC circuit 12 that senses the voltage VDDE across the power supply rails of the circuit being protected, and a clamping FET 14 whose gate is connected to the RC circuit 12. When there is a rapid rise in the voltage VDDE across the power supply rails, as might be caused by an ESD event, the clamping FET 14 is turned on, to shunt the large resulting current to ground before it can reach the circuit being protected.
In this basic type of clamping circuit, the time period for which the protection device maintains its protection is of a shorter duration than the complete ESD event. This is due to the fact that the gate voltage of the clamping FET 14 is coupled to the supply rail voltage VDDE. As the ESD voltage decays, the voltage at the gate decreases, thereby weakening the shunting capability of the FET 14. The FET 14 may turn off before the effects of the ESD have fully dissipated. In this case, the ESD current will continue to flow into the protected device, causing the voltage VDDE of the power supply to increase. If left unclamped, the voltage can rise beyond a maximum threshold, and the protected device can still be damaged.
To overcome this deficiency, a second timing circuit has been added to some prior art devices to maintain the duration of protection and hold the clamping circuit on for a longer period of time. An example of such a device is shown in FIG. 2. The operation of the second timing circuit 26, which consists of the gate capacitance of the FET 24 and the resistor 22, is also dependent upon the voltage VDDE across the supply rails, and hence the possibility still exists that the clamping FET 24 may turn off before the ESD event has terminated.
As a result of the failure to completely dissipate the ESD event, the voltage bus may remain charged. If a second ESD event should occur shortly after the initial one, the bus will not have the capacity to absorb some of the voltage, due to its charged state. The clamping circuit 20 must therefore handle all of the current of the subsequent ESD event, which increases the likelihood that protected circuit components could be damaged.